Surface Mount Packaging Reduces PCB Design Difficulty

Surface mount advanced packaging evolved from through-hole pin insertion packaging. Its main advantage is reducing the difficulty of PCB circuit board design, while also significantly reducing its own physical size. Chips soldered using this method are very difficult to remove without specialized tools. Surface mount packaging can be classified by pin position as follows: Single-ended (pins on one side), Dual (pins on two sides), Quad (pins on four sides), Bottom (pins on the bottom), BGA (pins arranged in a matrix structure), and others.

Single-ended

This packaging form features all pins on one side, with a relatively small number of pins. It can be further divided into: heat-dissipation type, such as commonly used power transistors, which have only three pins arranged in a row with a large heat sink on top; COF involves directly attaching the chip onto a flexible circuit board (using Flip-Chip technology in current applications), followed by plastic encapsulation. It is characterized by being lightweight and very thin, so it is now widely used in LCD (Liquid Crystal Display) panels to meet the needs of increasing LCD resolution. Its drawbacks are that the film material is very expensive, and the placement machine is also very costly.

Dual

This packaging form features all pins on two sides, with a moderate number of pins. It has many sub-forms, which can be further divided into SOT, SOP, SOJ, SSOP, HSOP, and others.

The SOT series mainly includes SOT-23, SOT-223, SOT25, SOT-26, SOT323, SOT-89, etc. As electronic products continue to shrink in size, the semiconductor devices used inside them must also become smaller. Smaller semiconductor devices enable electronic products to be smaller, lighter, more portable, and to contain more functions within the same size. SOT packaging greatly reduces both height and significantly decreases the PCB footprint.

Small Outline Package (SOP)

Philips developed the Small Outline Package (SOP) in the 1970s, which gradually evolved into SOJ (J-lead Small Outline Package), TSOP (Thin Small Outline Package), VSOP (Very Small Outline Package), SSOP (Shrink Small Outline Package), TSSOP (Thin Shrink Small Outline Package), SOT (Small Outline Transistor), SOIC (Small Outline Integrated Circuit), and others. SOP pin counts are typically within a few dozen pins.

Thin Small Outline Package (TSOP)

Its main difference from SOP is its very thin profile, only 1mm thick, which is 1/3 the thickness of SOJ. Due to its slim and lightweight appearance, it is suitable for high-frequency applications. It has won over the industry with its strong operability and high reliability. Most SDRAM memory chips use this TSOP packaging method. The TSOP memory package has a rectangular shape with I/O pins surrounding the encapsulated chip. In the TSOP packaging method, the memory chips are soldered onto the PCB through the chip pins. The contact area between the solder joints and the PCB is relatively small, making heat transfer from the chip to the PCB relatively difficult. Moreover, TSOP-packaged memory generates significant signal interference and electromagnetic interference when operating above 150MHz.

J-Lead Small Outline Package (SOJ)

Pins are led out from both sides of the package body in a J-shape, directly adhering to the surface of the printed circuit board. They are typically plastic products, mostly used for DRAM and SRAM memory LSI circuits, with the majority being DRAM. Many DRAM devices with SOJ packaging are assembled on SIMMs. Pin center spacing is 1.27mm, with pin counts ranging from 20 to 40.

Quad Flat Package (QFP)

QFP evolved from SOP. Its flat-shaped body has pins extending from all four sides in a gull-wing (L) shape. One end of the gull-wing-shaped lead terminals extends from the package body, while the other end is arranged on all four sides in the same plane. It is not mounted by inserting pins into through-holes on the printed circuit board (PWB), so there is no need to drill holes in the motherboard. Instead, it uses SMT (Surface Mount Technology) to attach to the PWB through solder. Generally, corresponding pad positions are designed on the motherboard surface. By aligning the package pins with the corresponding pads, soldering to the motherboard can be achieved. Therefore, circuits can be formed on both sides of the PWB. Using reflow soldering and other methods, all components mounted on both sides can be bonded in a single pass, facilitating automated operations and ensuring assembly reliability. This is currently the most widely adopted packaging form.

This type of packaging has very small spacing between pins and very fine leads. Generally, large-scale or very-large-scale integrated circuits adopt this packaging form. Its pin count typically ranges from several dozen to several hundred, and its package outline dimensions are relatively small with reduced parasitic parameters, making it suitable for high-frequency applications. This packaging is primarily suitable for installation and routing on PCBs using SMT surface mount technology. However, since QFP leads are arranged on all four sides and extend beyond the package body, if the lead spacing is too narrow and the leads too fine, the terminals are inevitably prone to deformation during manufacturing and assembly processes. When the number of terminals exceeds several hundred and the terminal spacing is equal to or less than 0.3mm, it becomes extremely difficult to precisely place them on the circuit pattern and complete assembly in a single pass together with other circuit components using reflow soldering, resulting in a dramatic increase in cost, as well as reliability and yield issues. Packaging forms such as PLCC with J-shaped lead terminals can alleviate some of these problems but cannot fundamentally solve the above-mentioned issues of QFP. Package forms derived from QFP include LCCC, PLCC, and TAB, among others.

The base materials for this packaging are ceramic, metal, and plastic. In terms of quantity, plastic packaging accounts for the vast majority. When no material is specifically indicated, it is usually plastic QFP. Plastic QFP is the most widely used multi-pin LSI package. The disadvantage of QFP packaging is that when the pin center spacing is less than 0.65mm, the pins are prone to bending. To prevent pin deformation, several improved QFP variants have been introduced.

Plastic Quad Flat Package (PQFP)

Pins are present on all four sides of the chip, with pin counts generally above 100. The spacing between pins is very small and the leads are very fine. Generally, large-scale or very-large-scale integrated circuits adopt this packaging form. Chips packaged in this form must use Surface Mount Technology (SMT) to solder the pins on the edges of the chip to the motherboard. PQFP packaging is suitable for SMT surface mount technology installation and routing on PCBs, suitable for high-frequency applications, and has advantages such as convenient operation, high reliability, and a relatively small ratio of chip area to package area.

Plastic Leaded Chip Carrier (PLCC) with pins. It is similar to LCC, except that the pins extend from all four sides of the package in a T-shape, and it is a plastic product. Pin center spacing is 1.27mm, with pin counts from 18 to 84. J-shaped pins are not easily deformed and are easier to handle than QFP, but post-soldering visual inspection is more difficult. The only difference between it and LCC packaging is that the former uses plastic while the latter uses ceramic, but now ceramic J-lead packages and ceramic-less pin packages made of plastic have also emerged.

Leadless Chip Carrier (LCC) or Quad Flat No-leads Package (QFN). Refers to surface-mount packaging where the four sides of the ceramic substrate have only electrode contacts without pins. Due to the absence of pins, the mounted area is smaller than QFP, and the height is lower than QFP. It is used for high-speed and high-frequency IC packaging. However, when stress occurs between the printed board and the package, it cannot be relieved at the electrode contacts, so the number of electrode contacts is difficult to match that of QFP pins, generally ranging from about 14 to 100. Materials include both ceramic and plastic. When marked as LCC, they are essentially ceramic QFN. Plastic QFN uses glass epoxy resin as the substrate material and is a low-cost packaging solution.

Ball Grid Array (BGA)

After more than a decade of development, BGA packaging has entered the practical stage and has become the most popular packaging technology.

With the development of integrated circuit technology, the requirements for IC packaging have become increasingly stringent. This is because packaging is directly related to product performance. When the IC frequency exceeds 100MHz, traditional packaging methods may produce so-called "Cross-Talk Noise" phenomena. Moreover, when the IC pin count exceeds 208 pins, traditional packaging methods face significant difficulties. Therefore, in addition to using QFP packaging, most high-pin-count chips today have switched to BGA packaging. Since its introduction, BGA has become the optimal choice for CPUs and high-pin-count packaging. BGA-packaged devices are predominantly used in mobile phones, networking and communication equipment, digital cameras, microcomputers, notebook computers, PADs, and various flat-panel displays in the high-end consumer market.

Advantages of BGA packaging include: 1. The number of input/output pins is greatly increased, and the pin spacing is much larger than QFP. Combined with its automatic alignment function with circuit patterns, assembly yield is improved. 2. Although power consumption increases, it can be soldered using controlled collapse chip connection (C4) methods, thereby improving its electrical and thermal performance. For chips with high integration and high power consumption, ceramic substrates are used with micro fans installed on the housing for heat dissipation, ensuring stable and reliable circuit operation. 3. The package body thickness is reduced by more than 1/2 compared to ordinary QFP, and the weight is reduced by more than 3/4. 4. Parasitic parameters are reduced, signal transmission delay is smaller, and the operating frequency is greatly improved. 5. Assembly can use coplanar soldering, resulting in high reliability.

Shortcomings of BGA packaging: BGA packaging, like QFP and PGA, still occupies a large substrate area. The warpage issue of plastic BGA packaging is its main defect, namely the coplanarity issue of solder balls. The coplanarity standard requires research into plastic materials, die-attach adhesives, and substrate materials to optimize these materials and reduce warpage while improving BGA packaging characteristics. At the same time, the high cost of substrates makes the overall price very high.

Tiny Ball Grid Array (Tiny-BGA)

Its difference from BGA packaging lies in the reduced chip area, which can be considered an ultra-miniature BGA package. However, compared to BGA packaging, it has three major improvements: the reduced package body allows for higher assembly density on the printed circuit board; the shorter path between chip and substrate reduces electromagnetic interference noise, enabling it to support higher operating frequencies; and it provides better heat dissipation performance.

Micro Ball Grid Array (mBGA). It is an improved version of BGA. The package body is square-shaped, occupying a smaller area with shorter connections, better electrical performance, and less susceptibility to interference. Therefore, this packaging provides better heat dissipation and overclocking performance, but the manufacturing cost is extremely high.